The invention lies in the integrated technology field. More specifically, the invention relates to a vertical MOS transistor with a particularly small channel length and good radiofrequency and logic properties.
With a view to ever-faster components with higher integration density, the structure sizes of integrated circuits are decreasing from generation to generation. This holds equally true in the context of CMOS technology. It is generally expected (see, for example, Roadmap of Semiconductor Technology, Solid State Technology 3, (February 1995)) that MOS transistors with a gate length of less than 100 nm will be used by the year 2010.
Attempts have been made, on the one hand, to scale customary modern CMOS technology in order to develop planar MOS transistors with such gate lengths (see, for example, A. Hori, et al., xe2x80x9cA 0.05 xcexcm-CMOS with Ultra Shallow Source/Drain Junctions Fabricated by 5 keV Ion Implantation and Rapid Thermal Annealing,xe2x80x9d IEDM 1994, 485; and H. Hu, et al., xe2x80x9cChannel and Source/Drain Engineering in High-Performance Sub-0.1 xcexcm NMOSFETs Using X-Ray Lithography,xe2x80x9d Symposium on VLSI Technology, 17, 1994)). The production of such planar MOS transistors with channel lengths of less than 100 nm requires the use of electron beam lithography and has hitherto been possible only on a laboratory scale. The use of the electron beam lithography leads to a more than proportional increase in production costs.
In parallel with those efforts, vertical transistors are being investigated. Since the channel length extends vertically in relation to a surface of a substrate, the surface area of a vertical transistor can be smaller than that of conventional planar transistors. A further reduction in area is obtained by reducing the channel width required for a given current, by shortening the channel length. Risch et al., in xe2x80x9cVertical MOS Transistor with 70 nm Channel Length,xe2x80x9d ESSDERC 1995, pages 101-04, describe vertical MOS transistors with short channel lengths. In order to produce those vertical MOS transistors, layer sequences are formed corresponding to the source, channel and drain, and are annularly surrounded by the gate dielectric and gate electrode. The channel lengths of vertical MOS transistors are small compared with those of conventional planar transistors. In terms of their radiofrequency and logic properties, vertical MOS transistors have to date been unsatisfactory in comparison with planar MOS transistors. This is attributable, on the one hand, to parasitic capacitances of the overlapping gate electrode and, on the other hand, to the formation of a parasitic bipolar transistor in the vertical layer sequence.
H. Takato et al. IEDM 88, pages 222-25 describes a vertical MOS transistor whose gate electrode annularly surrounds a cuboid layer structure in which a first source/drain region and a channel layer are arranged. The annular arrangement of the gate electrode increases the space-charge zone, which leads to a reduction in the stray capacitance. The channel length of the MOS transistor is large and corresponds to that of conventional planar transistors. The layer structure is produced using a lithographic method, and preferably has a lateral width of about 1 xcexcm, so that the space-charge zone fills the entire channel layer. The radiofrequency and logic properties of the vertical MOS transistor are therefore comparable with those of planar MOS transistors.
The object of the invention is to provide a method of producing a vertical MOS transistor which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this kind, and in which the radiofrequency and logic properties of the vertical MOS transistor are made comparable with those of planar MOS transistors, and the channel length of the vertical MOS transistor is made particularly small.
With the above and other objects in view there is provided, in accordance with the invention, a method of producing a vertical MOS transistor, which comprises:
providing a substrate of semiconductor material having a surface defining an axis extending perpendicularly to the surface;
forming a layer structure on the substrate with an etching process in which a spacer is used as a mask;
the layer structure having mutually opposite flanks extending parallel to the axis and including at least one first source/drain region and a channel layer below the first source/drain region relative to the axis;
forming a gate dielectric and a gate electrode at least in an area of the channel layer on the mutually opposite flanks of the layer structure; and
forming a second source/drain region below the channel layer relative to the axis.
In other words, the vertical MOS transistor is formed with a first source/drain region and a channel layer as parts of a layer structure. At least in the area of the channel layer, the layer structure is provided on at least two sides, i.e. at least on two opposite flanks of the layer structure, with a gate dielectric and a gate electrode. A first part of the gate electrode, which is next to a first of the two opposite flanks, and a second part of the gate electrode, which is next to a second of the two opposite flanks, are connected to one another, e.g. via a contact or a web. The gate electrode may also be formed continuously. In contrast to a one-sided arrangement, with the two-sided arrangement the channel width is doubled, without the surface area of the vertical MOS transistor therefore being increased, and the current is thereby increased and the formation of space-charge zones between the two flanks in the channel layer is enhanced. This is advantageous since, in space-charge zones, no leakage currents are created owing to a parasitic bipolar transistor.
Space-charge zones become commensurately larger as the dopant concentration in the channel layer is reduced. However, since the intention is to produce a short channel length, the channel layer must be heavily doped in order to avoid leakage currents due to punch-through. In order to obtain a space-charge zone throughout the channel layer, a dimension between the two opposite flanks of the layer structure must accordingly be particularly small. To that end, the layer structure is produced with the aid of a spacer acting as a mask. The dimension between the two opposite flanks of the layer structure becomes so small that, when the gate electrode is driven appropriately, the vertical MOS transistor becomes fully depleted. With a conventional voltage of from 0V-2V, the dimension is about 30 nm to 90 nm.
A second source/drain region may be arranged as part of the layer structure under the channel layer. It is advantageous if the second source/drain region is not part of the layer structure, but is produced essentially laterally with respect to the layer structure. As a result of this, on the one hand, the heavily doped first source/drain region and the heavily doped second source/drain region can be produced in self-aligned fashion by implantation, i.e. without using masks to be aligned. The first source/drain region is in this case arranged over the channel layer. On the other hand, the channel layer can be connected to a substrate of semiconductor material, which prevents floating-body effects in the channel layer should the latter not be fully depleted. In this case, the substrate is doped with the conductivity type of the channel layer in a layer next to the channel layer. The conductivity type of the layer may, however, also be chosen independently of the conductivity type of the channel layer. The conductivity type of the first source/drain region and of the second source/drain region can be swapped with the conductivity type of the channel layer.
The second source-drain region may also be formed as part of the layer structure, and/or adjoin the channel layer from below.
It is within the scope of the invention to produce the layer structure by structuring a layer sequence. For the layer sequence, at least one first layer doped with a second conductivity type is produced for the channel layer, and a second layer doped with a first conductivity type, which is the opposite of the second conductivity type, is produced for the first source/drain region. If the vertical MOS transistor is intended to be integrated in a circuit arrangement having a plurality of components, then it may be favorable to produce extra layers for the layer sequence.
The layer sequence can be produced over the entire surface of the substrate by epitaxial growth of in-situ doped semiconductor material. It is also possible to produce an indentation in the substrate, in which the layer sequence is produced by epitaxial growth. It is also possible, on the surface, to deposit a material in which an indentation extending as far as the surface is produced, and to produce the layer sequence by epitaxial growth in this indentation. If the layer sequence is grown epitaxially in an indentation, facets are formed at edges of the indentation since, at these edges, the growth rate is slower with selective epitaxy. The layers therefore become particularly thin, which leads to an especially small channel length. The layer sequence can also be produced by implantation with, in each case, differently charged ions and different ranges. In this case, epitaxial growth is not necessary and the substrate can be structured in order to produce the layer sequence. The layer sequence may contain a silicon layer and/or an Si(1xe2x88x92x)Gex layer.
In accordance with an added feature of the invention, therefore, the spacer is formed by:
producing a first auxiliary layer and structuring the first auxiliary layer with the aid of a first mask in such a way as to form an edge; and
subsequently producing a second auxiliary layer and etching the second auxiliary layer back to create the spacer from the second auxiliary layer, next to the edge of the first auxiliary layer.
In accordance with an additional feature of the invention, the step of forming the layer structure comprises structuring a layer sequence and forming a first layer doped with a second conductivity type for the channel layer and forming a second layer doped with a first conductivity type, which is the opposite of the second conductivity type, for the first source/drain region.
In accordance with another feature of the invention, wherein the first layer and then the second layer are epitaxially grown surface-wide above the surface, and the first auxiliary layer is subsequently produced above the second layer in relation to the axis.
It should be understood that expressions such as xe2x80x9ca is above bxe2x80x9d or xe2x80x9ca is below bxe2x80x9d does not necessarily mean that the two members or features are directly adjacent one another. Additional structure, i.e., something else, may be arranged between a and b.
In order to produce the spacer, it is advantageous to form an edge along which the spacer is created by depositing material and etching it back. The edge can be produced by depositing and structuring a first auxiliary layer above the layer sequence. The edge can also be created by masked etching of the layer sequence.
The layer structure may be formed in web form. It is within the scope of the invention if the layer structure is formed along a dividing line of a square or circular inner area of the substrate. To that end, the edge may be formed in such a way that one surface of the inner area lies deeper than its surroundings or higher than its surroundings. It is within the scope of the invention to form the layer structure along a complicated line pattern, e.g. the dividing lines of a rectangle together with web-like extensions on the sides of the rectangle.
It is advantageous to form the gate electrode as a spacer, so that the gate electrode becomes small and can be produced in self-aligned fashion.
In order to make contact with the gate electrode, it is advantageous to remove a part of the second layer in one area of the layer structure. In this area, contact is then made with the gate electrode using a first contact. Since the part of the second layer has been removed in this area, the formation of an undesired capacitance between the gate electrode and the first source/drain region is prevented. For the case in which the layer structure is formed along the dividing line of the inner area, a part of the gate electrode in the inner area is electrically connected with a part of the gate electrode outside the inner area by means of this contact. The gate electrode is formed continuously.
In order to form the gate electrode continuously, instead of this, a part of the layer structure may be removed so that the layer structure does not fully enclose the inner area. By depositing and etching back polysilicon, the gate electrode is thereby formed continuously.
As an alternative, the part of the gate electrode in the inner area and the part of the gate electrode outside the inner area may be connected by producing a conductive structure that adjoins, in a U-shape, the two opposite flanks and a surface of the layer structure which is at right angles in relation to the two opposite flanks. In order to prevent formation of the undesired capacitance between the gate electrode and the first source/drain region, it is advantageous in this case not to remove the spaces in one area, to produce extra spacers which cover the flanks of the layer structure and to produce the U-shaped conductive structure in this area. As a result, the distance between the U-shaped conductive structure and the first source/drain region is made large and the associated capacitance is made small. The U-shaped conductive structure can be produced at the same time as the gate electrode by depositing material and, with the aid of a mask which covers the area, etching it until the gate electrode is created in the form of a spacer. An unetched part of the material forms the U-shaped conductive structure.
In order to reduce the area of the vertical MOS transistor, it is advantageous to arrange a third contact of the second source/drain region inside the inner area. To that end, the second source/drain region is formed in such a way that a first part of the second source/drain region coincides with the inner area. After the gate electrode has been produced insulating material is deposited and etched back, by means of which a first insulating structure is created in the form of spacers that cover the gate electrode. The first part of the second source/drain region in the inner area is in this case partially exposed. A third contact is formed on the first part of the second source/drain region by depositing and etching back conductive material. At the same time, a second contact which makes contact with the first source/drain region is also formed.
Before making contact with the second source/drain region and the first source/drain region, it is advantageous to deposit and silicize metal.
A metal silicide contact structure created in this case reduces the electrical resistance at the junction between the respective source/drain region and the associated contact.
In order to simplify the production process, it is advantageous to use different insulating materials for insulating structures and for a protective layer which are next to one another, so that etching steps can be carried out selectively.
In order to make better contact with the first source/drain region, it is advantageous to produce the layer structure in such a way that it is particularly wide in one area. To that end, a mask covers this area when the spacer is being produced.
It is advantageous to produce a protective layer over the second source/drain region in order to reduce the capacitance formed by the gate electrode and the second source/drain region.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for producing a vertical MOS transistor, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.